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Video, speech, handwriting, virtual reality, Continue quadrupling memory about every 3 years, These improvements will create the need for new, Execution time and performance are reciprocals, Suppose that enhancement E accelerates a fraction. After you enable Flash, refresh this page and the presentation should play. 18-447 Introduction to Computer Architecture, Spring 2021 Announcements As in previous terms, 18-447 labs must be completed in groups of 2 or 3 students in Spring 2021. I/O data transfer or synchronization method, I/O Interface, I/O controller or I/O bus adapter, To the CPU, and I/O device, it consists of a set, On the I/O device side, it forms a localized I/O, Handles I/O details (originally done by CPU) such, Accepting or providing words in word-sized I/O, Should offer very high-speed (bandwidth) and low, Matched to the memory system performance to, Alpha EV6 (AMD K7), Peak bandwidth 400 MHz x 8, Intel GTL (P3), Peak bandwidth 133 MHz x 8 1, Intel P4, Peak bandwidth 800 Mhz x 8 6.4 GB/s, I/O buses (sometimes called an interface), Usually formed by I/O interface adapters to, Wide range in the data bandwidth and latency, Not usually interfaced directly to memory instead, Main system I/O bus PCI, PCI-X, PCI Express, Option High performance Low cost/performance, Bus width Separate address Multiplex address, Data width Wider is faster Narrower is cheaper, Transfer size Multiple words has Single-word, Bus masters Multiple Single master (requires, Programmed I/O (PIO) Polling (For low-speed, The I/O device puts its status information in a, The processor must periodically check the status, The processor is totally in control and does all, Used for low-speed I/O devices (mice, keyboards, Interrupt-Driven I/O (For medium-speed I/O), An interrupt line from the I/O device to the CPU, The interrupting device places its identity in an, Once an I/O interrupt is detected the current. - Computer Architecture Lecture 1 Computer Organization and Design (third edition) David A. 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The course objective is to gain the knowledge, Textbook Hennessy and Patterson, Computer, Fundamentals of Computer Architecture (Chapter 1), Instruction Set Architecture (Chapter 2, Appendix, Exploiting ILP with Software Approaches (Chapters, Plus, several computer architecture research, Scientific (FP intensive) / Commercial (Integer, Increase in communication and multimedia support, Decreases in feature size, increase in wafer, Computer architecture advances improves low-end, Putting performance growth in perspective, Many applications I/O limited, not computation, Processors speeds increase faster than memory and. Or use it to upload your own PowerPoint slides so you can share them with your teachers, class, students, bosses, employees, customers, potential investors or the world. All instructions require an instruction fetch, Optimize instruction access over data access, - Temporal Locality (items referenced recently), - Spatial Locality (items referenced nearby), Provide a storage hierarchy such that the most, The simple case is usually the most frequent and, Do simple, fast things in hardware and be sure, Would you handled these in hardware or software, The number of instructions/program is called the, The average number of cycles per instruction is, The number of seconds per cycle is the clock, The clock rate is the multiplicative inverse of, For example, if a processor has a clock period of, MIPS Instruction Count / Time 106 Clock, Not effective for machines with different, Not effective for programs with different, Attempt to match average frequencies of real, Only average behavior represented in test, Collecting too much data but doing too little, Benchmarks manually translated to optimize, SPEC CINT92 (6 integer programs) and SPEC CFP92, Compiler flags can be set differently for, new set of programs SPEC CINT95 (8 integer, new set of programs SPEC CINT2000 (12 integer, Programs in C, C, Fortran 77, and Fortran 90, Measures performance of Java Virtual Machines, Measures performance of network file server (NFS), Measures performance of large, industrial, Meausre performance of graphics applications, For more information about the SPEC benchmarks, A fundamental rule in computer architecture is to, The most accurate measure of performance is the, Execution time is dependent on the number of, When designing computer systems, both cost and. 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How Computers Work. This course is taught in tandem with 141L . To view this presentation, you'll need to allow Flash. (which component creates a system performance, Partitioning of the computing engine into, Central Processing Unit (CPU) Control Unit, Memory Instruction (program) and operand (data), Input/Output (I/O) Communication between the, The I/O subsystem provides the mechanism for. U. Pompeu Fabra, Spain. Three copies of data, may exist in cache, CPU or I/O (DMA) may modify/access one copy while, With write-back cache, the operating system, Use write-through cache I/O receives updated, The operating system designates memory address, I/O processing computational requirements. - William Stallings Computer Organization and Architecture 6th Edition Chapter 1 Introduction Architecture & Organization 1 Architecture is those attributes of a system ... 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Used for moderate speed I/O (optical drives, Allows overlap of CPU processing time and I/O, Direct Memory Access (DMA) (For high-speed I/O), Implemented with a specialized controller that, The DMA controller becomes the bus master and, Interrupts are still used only on completion of, Allows more overlap of CPU processing time and. Computer Architecture and Organization pdf Notes – CAO pdf notes file Link: Complete Notes Note :-These notes are according to the R09 Syllabus book of JNTU.